A typical computer system comprises a motherboard, a system bus, and a plurality of "nodes" or devices coupled to the system bus. The system bus is used by the nodes to send information signals to the motherboard and to each other. Because a plurality of different nodes are coupled to the same bus, some bus coordination mechanism is needed in order to coordinate access to the bus by the nodes to prevent bus contention. This bus coordination function is usually performed by a bus arbiter. A bus arbiter controls access to the system bus by first receiving bus access requests from the various nodes, and then determining (usually by performing some arbitration algorithm) which node should gain control of the system bus. Thereafter, the arbiter sends a bus grant control signal to the selected node to grant control of the bus to that node. Once the selected node has control of the bus, it is free to use the bus to send information signals. When information transmission is complete, the node notifies the arbiter that it no longer needs the bus and, at that point, the arbiter deasserts the bus grant signal to take control of the bus away from the node.
In typical operation, the bus arbiter alternatingly grants the system bus to a number of different nodes. There are times, however, when only one node actively and repeatedly requests the bus. During these times, it would be desirable for the requesting node to "pipeline" its requests. Pipelining is a process by which a node chains together consecutive bus requests such that the bus grant signal from the arbiter to the requesting node does not change logic levels between the different bus requests. Pipelining is desirable because it eliminates dead-time on the bus between consecutive information transfers, which in turn, increases bus utilization and improves system performance.
Currently, pipelining is implemented by having the requesting node generate and manage two separate signals. A first signal is used to request the bus, and a second signal is used to indicate to the arbiter that the node is finished with the bus. Such a pipelining scheme, while functional, is cumbersome because it requires that the node and arbiter manage and process two separate signals. Ideally, pipelining should be implemented using only one signal from the node, with this one signal being used to both request the bus and to retain ownership of the bus. Currently, however, there is no bus system believed to be available which has the ability to pipeline bus requests using only one signal from the requesting node.